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<b:Sources SelectedStyle="" xmlns:b="http://schemas.openxmlformats.org/officeDocument/2006/bibliography"  xmlns="http://schemas.openxmlformats.org/officeDocument/2006/bibliography" >
<b:Source>
<b:Tag>brucker:verifikation:2000</b:Tag>
<b:SourceType>Report</b:SourceType>
<b:Institution>Albert-Ludwigs-Universit&#228;t Freiburg</b:Institution>
<b:City>Freiburg</b:City>
<b:Year>2000</b:Year>
<b:Month>apr</b:Month>
<b:Author>
<b:Author><b:NameList>
<b:Person><b:Last>Brucker</b:Last><b:First>Achim</b:First><b:Middle>D</b:Middle></b:Person>
</b:NameList></b:Author>
</b:Author>
<b:Title>Verifikation von Dividierern mit Word-Level-Decision-Diagrams</b:Title>
<b:Comments>Late detection of design errors typically results in higher costs, therefore the importance of design verification and validation increases. This was especially shown in 1994 by the &#8220;Pentium bug&#8221;. Since then the effort put into the verification of arithmetic circuits, particularly division, has increased.\ In the area of the hardware verification decision diagrams are the most important data structures for the representation of boolean functions. However, in 1998 was shown that the representational power of any known decision diagram ist too weak to efficiently represent division.\ In this work a new approach for the verification of divider circuits is introduced, which by a transformation avoids the representation of the division operation as decision diagram. With this approach it was the first time possible to verify the nonrestoring division automatically only by the application of decision diagrams.</b:Comments>
</b:Source>
</b:Sources>